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cy62148esl mobl ? 4-mbit (512 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-50045 rev. *c revised august 23, 2010 4-mbit (512 k 8) static ram features higher speed up to 55 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 32-pin shrunk thin small outline package (stsop) package functional description the cy62148esl is a high performance cmos static ram organized as 512 k words by 8- bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption. placing the device in standby mode reduces power consumption by more than 99 percent when deselected (ce high). the eight inpu t and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the locati on specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. for best practice recommendati ons, refer to the cypress application note an1064, sram system guidelines . a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 512k x 8 array input buffer a 10 a 11 a 12 a 18 logic block diagram i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 2 of 13 contents 4-mbit (512 k 8) static ram .......................................... 1 features ............................................................................. 1 functional description ..................................................... 1 pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 data retention characteristics ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ........................................................................ 9 ordering information ...................................................... 10 ordering code definitions ...... ....................................... 10 package diagram ............................................................ 11 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 3 of 13 pin configuration figure 1. 32-pin stsop (top view) 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 a 11 a 9 a 8 a 13 a 17 a 15 a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 we v cc 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 a 0 a 1 a 2 a 3 a 10 oe ce i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd stsop top view (not to scale) product portfolio product range v cc range (v) [1] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( a) f = 1 mhz f = f max typ [2] max typ [2] max typ [2] max cy62148esl industrial/ automotive-a 2.2 v to 3.6 v and 4.5 v to 5.5 v 55 2 2.5 15 20 1 7 notes 1. datasheet specifications are not guaranteed for v cc in the range of 3.6 v to 4.5 v. 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 4 of 13 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied.... 55 c to +125 c supply voltage to ground potential................. ?0.5 v to 6.0 v dc voltage applied to outputs in high z state [3, 4] ......................................... ?0.5 v to 6.0 v dc input voltage [3, 4] ..................................... ?0.5 v to 6.0 v output current into outputs (l ow)..................................20 ma static discharge voltage .......................................... > 2001 v (mil-std-883, method 3015) latch-up current......................................................> 200 ma operating range device range ambient temperature v cc [5] cy62148esl industrial/ automotive-a ?40 c to +85 c 2.2 v to 3.6 v, and 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 55 ns (industria l/automotive-a) unit min typ [6] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il [7] input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.4 v 2.7 < v cc < 3.6 ?0.3 ? 0.6 4.5 < v cc < 5.5 ?0.5 ? 0.6 i ix input leakage current gnd < v i < v cc ?1 ? +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma, cmos levels ?15 20ma f = 1 mhz ? 2 2.5 i sb1 [8] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe and we ), v cc = v cc(max) ?1 7 a ? i sb2 [8] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?1 7 a ? notes 3. v il (min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 6. typical values are included for reference and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 7. under dc conditions the device meets a v il of 0.8 v (for v cc range of 2.7 v to 3.6 v and 4.5 v to 5.5 v) and 0.6 v (for v cc range of 2.2 v to 2.7 v). however, in dynamic conditions input low voltage applied to the device must not be higher than 0.6 v and 0.4 v for the above ranges. refer to an13470 for details. 8. chip enable (ce ) must be high at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 5 of 13 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc (typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions stsop unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 49.02 c/w jc thermal resistance (junction to case) 14.07 c/w figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 parameter 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 r2 15385 1554 990 r th 8000 645 639 v th 1.20 1.75 1.77 v notes 9. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 6 of 13 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [11] data retention current ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, v cc = 1.5 v industrial/ automotive-a ?17a t cdr chip deselect to data retention time 0??ns t r [12] operation recovery time 55 ? ? ns figure 3. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce notes 10. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enable (ce ) must be high at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 7 of 13 switching characteristics over the operating range parameter [13] description 55 ns (industria l/automotive-a) unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [14] 5?ns t hzoe oe high to high z [14, 15] ?20ns t lzce ce low to low z [14] 10 ? ns t hzce ce high to high z [14, 15] ?20ns t pu ce low to power-up 0 ? ns t pd ce high to power-up ? 55 ns write cycle [16] t wc write cycle time 55 ? ns t sce ce low to write end 40 ? ns t aw address setup to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 40 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [14, 15] ?20ns t lzwe we high to low z [14] 10 ? ns notes 13. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in ac test loads and waveforms on page 5 . 14. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 15. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates th e write. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 8 of 13 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [17, 18] figure 5. read cycle no. 2 (oe controlled) [18, 19] figure 6. write cycle no. 1 (we controlled, oe high during write) [20, 21] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 22 notes 17. device is continuously selected. oe , ce = v il . 18. we is high for read cycles. 19. address valid before or similar to ce transition low. 20. data i/o is high impedance if oe = v ih . 21. if ce goes high simultaneously with we high, the output remains in high impedance state. 22. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 9 of 13 figure 7. write cycle no. 2 (ce controlled) [23, 24] figure 8. write cycle no. 3 (we controlled, oe low) [24] truth table ce we oe i/o mode power h [26] x x high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l h h high z output disabled active (i cc ) l l x data in write active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 25 notes 23. data i/o is high impedance if oe = v ih . 24. if ce goes high simultaneously with we high, the output remains in high impedance state. 25. during this period, the i/os are in output state. do not apply input signals. 26. chip enable (ce ) must be high at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 10 of 13 ordering information ta b l e 1 lists the cy62148esl mobl key package features and ordering codes. the table contains only the parts that are currently available. if you do not see what you are looking for, contact y our local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions table 1. key features and ordering information speed (ns) ordering code package diagram package type operating range 55 cy62148esl-55zaxi 51-85094 32-pin stsop (pb-free) industrial CY62148ESL-55ZAXA 51-85094 32-pin stsop (pb-free) automotive-a cy family: low power sram 621 4 8 density = 4 mbit company id: cy = cypress e bus width = x8 process technology: 90-nm sl sl = low power 55 speed grade (55 ns) zax 32-pin stsop (pb-free) i/a temperature grades: i = industrial a = automotive-a [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 11 of 13 acronyms document conventions units of measure package diagram figure 9. 32-pin shrunk thin small ou tline package (8 mm 13.4 mm), 51-85094 51-85094-*e acronym description cmos complementary metal oxide semiconductor i/o input/output mobl more battery life sram static random access memory stsop shrunk thin small outline package symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes pf pico farad c degree celsius wwatts [+] feedback
cy62148esl mobl ? document #: 001-50045 rev. *c page 12 of 13 document history page document title: cy62148esl mobl ? 4-mbit (512 k 8) static ram document number: 001-50045 revision ecn orig. of change submission date description of change ** 2612938 vkn/pyrs 01/21/09 new datasheet *a 2800124 vkn 11/06/2009 included automotive-a information *b 2947039 vkn 06/10/2010 added footnote related to chip enable in truth table added footnote for the i sb2 parameter in electrical characteristics updated package diagram updated links in sales, solutions, and legal information *c 3006318 aju 08/23/10 template update. updated table of contents. added acronyms, units of measure and ordering code definitions. added reference to note 8 to parameter i sb1 on page 4 under electrical characterisitics table. added reference to note 11 to parameter i ccdr on page 6 under data retention characteristics table. [+] feedback
document #: 001-50045 rev. *c revised august 23, 2010 page 13 of 13 mobl is the registered trademark, and more battery life is the trademark of cypress semiconductor corporation. all other produc t and company names mentioned in this document are the trademarks of their respective holders. cy62148esl mobl ? ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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